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TUESDAY
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OPENING SESSSION & KEYNOTE SPEAKER
8:30 - 10:00 | Ballroom 20ABC
Gigascale Integration for Teraops Performance--Challenges, Opportunities, and New Frontiers
Pat Gelsinger - Senior Vice President, Chief Technology Officer, Intel Corp. |
| BREAK 10:15 - 10:30 am |
| Ses# |
Business Day
Session 1 |
Session 2 |
Session 3 |
Session 4 |
Session 5 |
|
| 10:30 to 12:00 |
Panel: CEO PANEL: EDA: This is Serious Business |
Special Session: Management of HOT Leakage |
Clock Routing and Buffering |
Tools and Strategies for Dynamic Verification |
Timing-Driven System Synthesis |
| LUNCH Noon - 2 pm |
| Ses# |
Session 6 |
Business Day
Session 7 |
Session 8 |
Session 9 |
Session 10 |
Business Day
Session 100
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HoT
|
| 2:00 to 4:00 |
Special Session: Reliable Systems-on-a-Chip Design in the Nanometer Era |
Panel: When IC Yield Missed the Target, Who is at Fault? |
Power Modeling and Optimization for Embedded Systems |
Performance Evaluation and Run Time Support |
Advances in Analog Circuit and Layout Synthesis |
|
 |
| BREAK 4 - 4:30 pm |
| Ses# |
Session 11 |
Business Day
Session 12 |
Session 13 |
Session 14 |
Session 15 |
Business Day
Session 150 |
| 4:30 to 6:30 |
Power Grid Design and Analysis Techniques |
Panel: What Happened to ASIC? Go (Recon)figure? |
Methods for a Priori Feasible Layout Generation |
Abstraction Techniques for Functional Verification |
Memory and Network Optimization in Embedded Designs |
|
| 6:30 to 8:00 |
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